(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for making bipolar junction transistors (BJTs, hereafter also referred to as bipolar transistors) that are compatible with CMOS processes. The improved bipolar transistor results in increased current gain of the BJT while requiring only one additional implant mask.
(2) Description of the Prior Art
Typically the fabrication of bipolar and CMOS transistors on the same chip requires a considerable number of additional processing steps. Because of their vertical structure, bipolar transistors require a series of separate implant masks and ion implant steps for making the emitter, base, and collector. This is because the bipolar requires multiple masking and implant steps to form the collector, base, and emitter at different depths in the silicon substrate. On the other hand, the field effect transistors (FETs), such as used on dynamic random access memory (DRAM) circuits, are basically surface devices that are simpler to fabricate. However, for many circuit applications, it is desirable to be able to fabricate the bipolar transistors and FETs, commonly referred to as BiCMOS devices, on the same substrate with reduced complexity.
One problem in integrating bipolar transistors with CMOS devices is the low current gain (Ic/Ib about 25) of the bipolar transistor. To achieve high current gains (Beta) it is desirable to form the base as narrow as possible to reduce the electron-hole recombination in the base. One conventional type of bipolar transistor is shown in FIG. 1. In this approach a buried N+ region 12 is formed in a substrate 10 to form the transistor collector, and an Nxe2x88x92 doped epitaxial layer 14 is grown. Next, shallow trench isolation (STI) 16 is used to electrically isolate the device areas. Then the base 18 is implanted through the STI 16, and the STI is used to separate the base contact 18B from the implanted emitter region 20 to improve (increase) the emitter-to-base breakdown voltage. Unfortunately, the need to implant the base 18 through the STI 16 limits how thin the base can be made because it is necessary to implant through the STI to provide electrical continuity between the intrinsic base region 18 and the extrinsic base contact 18B.
The low current gain (Beta) (Ic/Ib) as a function of the log of the collector current Ic is shown by the curve 100 in FIG. 2. The Beta is limited to a maximum value of less than 25 because of the limit on the width W of the base 18 in FIG. 1.
Appel et al., U.S. Pat. No. 6,030,864, disclose a method of making a vertical NPN transistor for use with CMOS logic technology having minimum feature sizes of 0.35 micrometers. The method uses a patterned photoresist to separate the bipolar transistor collector and emitter implants when fabricating the P- and N-channel FETs. After removing the photoresist, a silicon nitride blocking layer is used between the collector, emitter, and base contacts during implanting to compensate for the high peripheral base doping. Walker et al., U.S. Pat. No. 6,130,117, describe a method for making a BiCMOS in which the bipolar transistor is used as a silicon controlled rectifier (SCR) to control electrostatic discharges that can damage the FETs. Walker et al. do not address the separation of the emitter and base, or the width of the base for improved Beta. U.S. Pat. No. 6,174,760 B1 to Cheng et al. describes a vertical PNP bipolar transistor in which the P type substrate serves as the collector, an N well in the substrate forms the base, and then a P dopant is implanted in the N well to form the emitter.
However, there is still a strong need in the semiconductor industry to make circuits having bipolar junction transistors (BJTs) having high current gain (Beta) integrated with CMOS devices (FETs) while providing a simple semiconductor process that reduces manufacturing cost.
A principal object of this invention is to make a high current gain (Beta) bipolar junction transistor by making a thinner bipolar transistor base which is compatible with a CMOS process.
Another object of this invention is to achieve thinner base widths by utilizing portions of the patterned polysilicon layer, used to make the FET gate electrode structure, as a polysilicon gate mask to form novel bipolar structures. The patterned polysilicon portions used in the bipolar transistor serve only as implant masks to separate the base contacts from the emitters.
A further objective of this invention is to use this sequence of process steps to reduce process complexity and manufacturing costs.
In accordance with the objects of this invention, a method for making a novel bipolar transistor structure, which is compatible with CMOS processing, is achieved. This novel process provides a method for making bipolar transistors with thinner base widths, and therefore increased current gain, while requiring only one additional implant mask over the more conventional process. The method is described for making an NPN bipolar transistor. By reversing the dopant polarity, it is also possible to form a PNP bipolar transistor.
The method consists of providing a substrate. The substrate is preferably a single-crystal-silicon wafer having a  less than 100 greater than  crystallographic orientation with respect to the substrate surface. A shallow trench isolation (STI) is formed in the substrate to electrically isolate and define device areas for the FETs and the bipolar transistors. Next the P wells and N wells for the respective CMOS N-channel and P-channel FETs are implanted. The P well implant also serves as the base of the NPN bipolar transistor. Then, a novel feature of this invention, is to use an implant mask to implant deep N+ wells to make the subcollectors in the desired device areas for the NPN bipolar transistors.
More specifically, the bipolar transistor is formed from two adjacent device areas, called first and second device areas. First wells of an N type dopant are formed for the transistor collector contacts in the first device areas. Second wells of a P type dopant are formed in the second device areas adjacent to the first device areas for the transistor base regions, separated by the STI regions. N type doped third wells are deeply implanted under the first wells and the second wells and under the STI regions to form the transistor subcollectors. A gate oxide is formed on the substrate. Next, a key feature of the invention is to deposit and pattern a polysilicon layer to form gate electrode masking elements over the transistor base regions to isolate the base contact regions from the emitter regions. The polysilicon is also concurrently patterned to form CMOS FET gate electrodes elsewhere on the substrate. First lightly doped drains of an N type dopant are formed for N channel FETs and in the transistor emitter regions. Next, second lightly doped drains of a P type dopant are formed for P channel FETs and in the transistor base contact regions. Sidewall spacers are then formed on the gate electrodes and are also formed on the gate electrode masking elements over the transistor base regions. After forming the sidewall spacers, source/drain areas of an N type dopant are formed for the N channel FETs, and concurrently heavily doped source/drain implants are also used to form emitters in the transistor base regions. Then heavily doped P type source/drain areas are formed for the P channel FETs, and are also used to form heavily doped base contacts in the base contact regions to provide good low ohmic contact for the bipolar transistor. By the method of this invention, the gate electrode masking elements are used to separate the emitters from the base contact regions to maximize the emitter-to-base breakdown voltage. The bipolar CMOS devices are then completed using conventional processing. For example, a first insulating layer is deposited to protect and electrically insulate the devices. Then contact openings are etched, and a first metal is deposited and patterned to form a level of electrical inter-connections.